A low power-delay-product hybrid cmos full adder design for chain and tree structures and its characterization

Abstract

Demand of portable electronic devices with high speed and longer battery life is increasing rapidly. Addition is one of the most frequently used operations in the Arithmetic and Logic Unit (ALU) of micro-processors. An adder (which performs this addition operation), is present in almost all digital electronic systems, ranging from general purpose processors to special purpose processors (DSP, Neuromorphic chips, etc). Addition is also indirectly used in subtraction, multiplication, division and address generation operations. Hence, an improvement in the performance of an adder, helps in improving the overall performance of the digital system. Full Adder (FA) is the basic building block used to construct multi-bit adders, multi-operand adders, multipliers etc. Our proposed work is focused on an improvement of FA design and its characterization. Initially, this thesis is focused on development of new input test pattern for characterization of the FA. A new input test pattern suggested here, is capable of estimating maximum propagation delay and average power dissipation, with reasonable number of input transitions. Further, the same input test pattern is expanded to characterize n-bit Ripple Carry Adder (RCA) in terms of maximum propagation delay and average power dissipation. The hybrid CMOS design style is the best approach when speed and power are both important to the designer. Two new hybrid CMOS FA designs are proposed in this thesis. These FAs are capable of achieving low power and high speed when used in the multi-bit adders (chain structure) and multipliers (tree structure). A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop a mathematical model (based on 2nd degree polynomial equations) of the FA is proposed here, which satisfactory estimates the Power-Delay-Product (PDP) of a FA for non-simulated parameter combinations within given parameter range. Main aim of the proposed method is to reduce characterization e ort by estimating PDP using mathematical model, rather than estimating it through simulations. Also, mathematical model can estimate the transistor widths required to achieve low PDP for particular operating condition. Further, we study the e ect of individual polynomial term, number of parameters and number of points per parameter, on the accuracy of the mathematical model. Finally, the thesis proposes a novel idea, a triplet design, to improve the PDP of transmission gate and hybrid CMOS FA designs in multi-bit adders and multipliers by reducing the load on initial carry signal. A triplet design approach eliminates the need of bu ers to restore the signal strength in multi-bit adders and multipliers designed using transmission gate and hybrid CMOS FA designs.